>> skills/boot-debug-config

stars: 0
forks: 0
watches: 0
last updated: 2026-03-21 16:24:14

Boot and Debug Configuration

Extract boot mode configuration and debug interface information from reference manual and programming manual PDFs.

What to Extract

Boot Modes

  • Boot mode selection mechanism (BOOT0/BOOT1 pins or option bytes nBOOT0/nBOOT1)
  • Boot mode table: pin/option byte combinations and resulting boot source
  • Boot addresses: Main Flash (0x08000000), System memory (bootloader), embedded SRAM
  • Boot address remapping (if available on the family)

System Memory Bootloader

  • Built-in bootloader location (System memory, factory-programmed by ST)
  • Supported bootloader protocols: USART, I2C, SPI, USB DFU, CAN, FDCAN
  • Which pins are used for each bootloader protocol
  • Bootloader version and supported commands

Debug Interfaces

  • SWD (Serial Wire Debug): SWDIO, SWCLK pins
  • JTAG: TMS, TCK, TDI, TDO, TRST pins (if applicable)
  • SWO (Serial Wire Output): trace pin for ITM/printf debugging
  • Debug port pin locations (which GPIO port/pins)

Debug Configuration

  • DBGMCU register: debug support during low-power modes
  • Freeze peripherals during debug (timers, watchdogs, RTC)

Where to Find This Information

Reference Manual - Boot Configuration

Glob pattern: docs/reference-manual/*.pdf

  1. Read pages 1-5 (ToC)
  2. Find section titled "Boot configuration" or "System memory boot mode" (often in chapter 2 or a dedicated boot chapter)
  3. Extract the boot mode selection table (BOOT0/BOOT1 -> boot source)
  4. Find "SYSCFG" chapter for memory remap register if applicable

Reference Manual - Debug

  1. From ToC find the "Debug support (DBG)" chapter (usually near the end)
  2. Contains DBGMCU_IDCODE (device ID), DBGMCU_CR (debug configuration)
  3. Lists which peripherals can be frozen during debug halt

Programming Manual

Glob pattern: docs/programming-manual/*.pdf

  1. Cortex-M programming manual contains debug port architecture details
  2. Look for "Debug port" or "CoreSight" sections
  3. Contains DAP (Debug Access Port) architecture, breakpoint/watchpoint configuration

Application Note AN2606 (Bootloader)

Glob pattern: docs/application-notes/*2606* or docs/application-notes/*bootloader*

  1. AN2606 is the definitive bootloader reference for all STM32 families
  2. Contains per-device bootloader protocol availability
  3. Lists exact pins used for each protocol
  4. Documents bootloader activation conditions

Extraction Process

  1. Glob docs/reference-manual/*.pdf
  2. Read ToC (pages 1-5) to find boot configuration and debug chapters
  3. Read boot configuration section - extract boot mode table
  4. Read debug chapter - extract debug pins and DBGMCU registers
  5. Optionally glob docs/programming-manual/*.pdf for Cortex-M debug details
  6. Check docs/application-notes/ for AN2606 (bootloader documentation)
  7. Compile boot and debug configuration profile

Key Concepts

Boot Pin Behavior

On older families (F1, F4): Physical BOOT0 and BOOT1 pins sampled at reset. On newer families (L4+, G0, G4, H7): BOOT0 pin + option byte nBOOT0/nBOOT1 bits. Some families allow disabling BOOT0 pin entirely via option bytes.

System Memory Bootloader

Factory-programmed, cannot be erased. Activated when boot mode selects System memory. Supports a subset of interfaces depending on the MCU variant. Always check AN2606 for the specific device.

SWD vs JTAG

SWD uses 2 pins (SWDIO + SWCLK), JTAG uses 5 pins. SWD is preferred for most development (fewer pins, sufficient for most debugging). The pins are shared with GPIO (PA13/PA14 for SWD on most families). After reset, debug port is active; reconfiguring PA13/PA14 as GPIO disables debug access.

Output Format

## Boot Configuration

**Boot Mode Selection**: BOOT0 pin + option bytes
| BOOT0 | nBOOT1 | Boot Source |
|-------|--------|-------------|
| 0     | x      | Main Flash (0x08000000) |
| 1     | 0      | System Memory (bootloader) |
| 1     | 1      | Embedded SRAM |

**System Bootloader Protocols**: USART1 (PA9/PA10), USB DFU, I2C1

## Debug Interface

**SWD Pins**: PA13 (SWDIO), PA14 (SWCLK)
**SWO Pin**: PB3 (trace output)
**JTAG**: PA13 (TMS), PA14 (TCK), PA15 (JTDI), PB3 (TDO), PB4 (TRST)
**Device ID**: DBGMCU_IDCODE at 0xE0042000

Additional Resources

  • references/boot-debug-guide.md - Boot mode tables per family, debug pin assignments, OpenOCD and ST-Link configuration templates
    Good AI Tools